IMPROVING INTEGRATED CIRCUIT PERFORMANCE AND RELIABILITY USING A PATTERNED BUMP LAYOUT ON A POWER GRID

摘要

A method for improving integrated circuit by using a patterned bump layout on a metal layer of the integrated circuit is provided. The method creates various bump structures by varying an angle between a line from a reference bump to a first bump and a line from the reference bump to a second bump. By varying the angle, a designer may generate a particular bump structure that meets the needs of a particular design. Further, a particular bump placement may be repeated across all or a portion of the metal layer in order to create a patterned bump layout.