| 摘要 |
<p>In data communication between processors, it is possible to remove unnecessary data transfer between the processors, thereby eliminating lowering of performance. Moreover, in a multi-processor using an interleave cache, it is possible to prevent use efficiency lowering of the cache memory due to fixation of the interleave configuration. A multi-processor system includes a plurality of processors (50) having a data cache (26) and a main memory (13) which are connected to each other via a bus (10). The system has data transfer engine (11) having a region for storing information on data access and issuing a load instruction and a store instruction to the data cache (26) according to the information. Each of the processors (50) has judgment means (22) for storing information on sharing of the data cache and referencing this information upon reception of an address to be accessed, so as to judge which processor is to be accessed.</p> |
