MEMORY CONTROLLER STRUCTURE CAPABLE OF REMOVING CLOCK SKEW AND MEMORY DEVICE

摘要

PURPOSE: A memory controller structure capable of removing a clock skew and a memory device is provided to operate at a maximum frequency supplied by a synchronous dynamic random access memory(SDRAM) by using an interface block capable of overcoming the performance deterioration due to the skew between the clock signals. CONSTITUTION: A memory controller structure capable of removing a clock skew with a memory device includes a core logic(20) for generating a plurality of control signals and write signals supplied to the synchronous dynamic random access memory(SDRAM) device, a first interface block(30) for temporally storing the control signals and the write data from the core logic(20) in response to the first clock signal of the memory controller, a second interface block(40) for firstly latching the read data outputted from the synchronous memory device in response to the second clock signal synchronous with the first clock signal of the memory controller and for temporally storing the latched read data in response to the first clock signal and a third interface block(50) for generating the third clock signal supplied to the synchronous memory device in response to the first clock signal of the memory controller and for generating the second clock signal at the same time.