| 摘要 |
A laminated capacitor comprises interleaved dielectric (22) and electrode layers 10, 12 in an interdigitated configuration. Peripheral termination lands 24 are then applied to the sides (16), (18) of the multilayer configuratiuon to form electrical connections to exposed portions of the electrode layers 10, 12. Selected edges of the device are then preferably coated with a solder stop material 26. Solder balls 28 may be applied directly to the peripheral terminations lands 24, providing a ball grid array (BGA) packaged chip ready to mount on a printed wire board utilising solder reflow techniques. Composition of such solder balls 28 may be varied to comply with specific firing conditions. Such capacitor chips are also compatible with land grid array (LGA) packaging techniques. The interdigitated electrode design may be utilized to form a single multilayer capacitor or multiple discrete capacitors. Such a capacitor array may be formed by retaining the external configuration and internally subdividing the electrodes. The resulting capacitor may be utilised in high frequency applications requiring decoupling capacitors. |
