Channel compensator for DS-CDMA receiver

摘要

A channel compensator for estimating and for compensating a phase change and a residual frequency offset of a despreaded signal, prior to synchronous demodulation in a DS-CDMA receiver. In the channel compensator, a first integrator accumulates input signals sampled at a given chip rate for a predetermined period and multiplies the accumulated value by a given gain. A shift register having a plurality of registers shifts the data output from the first integrator. A second integrator integrates the data generated at once from the respective registers of the shift register. A delay means delays the input signal for a predetermined time, and a multiplier multiplies the delayed input signal by an output of the second integrator in order to generate the compensated signal. The delay device delays the input signal by a time required for the input signal to reach a central register of the shift register through the first integrator. The second integrator includes a summer means for summing the values of the respective registers of the shift register at an update period of the first integrator, and a multiplier for multiplying a value output from the summer means by a reciprocal number of the number of the registers to reduce the dispersion of an estimation value due to noises, and for adjusting a bit value for detected information.