| 摘要 |
When an input signal S11 is variable-gain-amplified by a variable gain amplifier 1 to obtain a predetermined output signal S12, a variable gain control signal S15 is generated by a detecting circuit 2, an A/D converter 3, an adder 4, and a converting unit 5. Both a latch circuit 6 and an adder 7 calculate a difference between a variable gain control signal generated during a preceding control operation and a present variable gain control signal. When the difference result is equal to "0", a counter 8 counts predetermined stable condition continued time, and thereafter outputs a non-operation setting signal S16. Also, the counter 8 sends out the variable gain control signal generated during the preceding control operation to the variable gain amplifier 1 so as to set the detecting circuit 2, the A/D converter 3, the adder 4, and the converting unit 5 into non-operation conditions thereof.
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