Clock forwarding circuit with automatic clock delay detection and initial parameter setting features

摘要

A clock forwarding circuit automatically detects the delay in transmission of data between a master circuit such as a central processing unit and a slave circuit such as a semiconductor memory and forwards clocks corresponding to the delay. The master circuit includes a clock forwarding circuit which generates a clock signal. The slave circuit is coupled to the master circuit and generates a second clock signal which is synchronized with the first clock signal. The clock forwarding circuit receives the second clock signal, detects delay between the first and second clock signals and sets initial data load/unload parameters of the master circuit based on the detected delay. By forwarding clocks, the data transmission between the clocked circuits can be performed in faultless fashion independently of the delay.