| 摘要 |
The present invention relates to a clock selection circuit which can eliminate short clock signals when switching clock signals produced by one clock generator to clock signals produced by another clock generator. The clock selection circuit comprises a selecting circuit for selecting the clock signals generated by a first clock generator out of a plurality of clock generators of different frequencies and generating an output, each clock signal comprising two different logic levels; a first detecting circuit for detecting a predetermined logic level contained in the output of the selecting circuit after receiving a clock selection signal wherein the selecting circuit is switched to select the clock signals generated by a second clock generator according to the clock selection signal after the predetermined logic level is detected by the first detecting circuit; a holding circuit for holding the output of the selecting circuit unchanged after the predetermined logic level being detected by the first detecting circuit; and a second detecting circuit for detecting the predetermined logic level contained in the output of the selecting circuit after the output of the selecting circuit being held by the holding circuit and releasing the holding circuit to allow the output of the selecting circuit to pass through when detected.
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