| 摘要 |
A cache memory control device enables an external instruction ROM to be co-owned by plural processors while minimizing the lowering of the processing performance of the processor and curtailing the number of external terminals of the LSIs. In a multi-processor system having a processor, an instruction RAM bank and an instruction RAM controller for each physical layer PHY, there is provided one instruction ROM for storing instruction data. The RAM controller of each PHY outputs time allowance information to a pre-fetch request of the instruction data. If there are simultaneously output pre-fetch requests from plural PHYs, the pre-fetch controller selects a pre-fetch request having the smallest time allowance.
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