发明名称 |
METHOD FOR FORMING MULTILAYER METAL WIRING |
摘要 |
PURPOSE: A method for forming a multilayer metal wiring is provided to be capable of minimizing the via resistance. CONSTITUTION: The first metal wiring(38) with the first width is formed on a semiconductor substrate(31) having a transistor. An IMD(InterMetal Dielectric)(39) is formed on the entire surface of the first metal wiring(38). After forming a photoresist pattern on the intermetal dielectric(39), a via hole having the second width is formed by selectively etching the intermetal dielectric(39) and the portions of the first metal wiring(38). At this time, the second width is relatively narrow compared to the first width. The second metal wiring(41) is formed in the via hole to contact the first metal wiring.
|
申请公布号 |
KR20030044449(A) |
申请公布日期 |
2003.06.09 |
申请号 |
KR20010075194 |
申请日期 |
2001.11.30 |
申请人 |
HYNIX SEMICONDUCTOR INC. |
发明人 |
KIM, SANG IK;LEE, SEONG GWON |
分类号 |
H01L21/3205;(IPC1-7):H01L21/320 |
主分类号 |
H01L21/3205 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|