| 摘要 |
PURPOSE: A power voltage level detector is provided to improve sensing margin and prevent misoperation due to noise by using difference voltage generator to increase change of comparison voltage according to voltage source variation. CONSTITUTION: A power voltage level detector includes a reference voltage generating block for generating a reference voltage having a predetermined level in response to a control signal, a comparative voltage generation block for generating a large voltage having a large change in comparison with the power voltage supplied from outside in response to the control signal and a comparing block for outputting a predetermined signal by comparing the reference voltage and the comparative voltage in response to the control signal. The comparative voltage generation block includes a first PMOS transistor(P11) connected the source thereof to the power voltage and operated in response to the control signal, a resistor(R11) connected between the drain of the first PMOS transistor(P11) and the node, a second PMOS transistor(P12) connected between the power voltage and the output terminal and operated in response to the control signal and an NMOS transistor(N11) connected between the output terminal and the ground.
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