| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a phase comparator and a clock generating circuit, which can compare a phase of a first clock signal with the one of a second clock signal accurately. <P>SOLUTION: A double phase comparator 6 makes both of signals ϕK and ϕD to L level and delays the phase of a feedback clock signal FBCLK when the feedback clock signal FBCLK in the leading edge and the trailing edge of an internal clock signal is H level and L level respectively. The double phase comparator 6 makes both of signals ϕK and ϕU to L level and advances the phase of the feedback clock signal FBCLK when the feedback clock signal FBCLK in both edges is L level and H level respectively. If the level of the feedback clock signal FBCLK in both edges matches, the double phase comparator 6 makes signal ϕK to H level and stops phase control of the feedback clock signal FBCLK. <P>COPYRIGHT: (C)2003,JPO |
