| 摘要 |
<p>A data processing circuit for a communication receiver comprises an input path (23), a control (27), a sign modifying module (29), first and second delay elements (31, 33), first and second multiplying means (35, 37) and a summing module (39). The control module (27) is arranged to generate control signals for controlling the operation of the sign modifying module (29), by means of control line (41), and the first and second multiplying means, by means of respective control lines (43, 45). In operation, input samples (e.g. from an ADC) are fed at a clock rate to an input of the sign modifying module (29). The sign modifying module (29) acts to modify the sign of the value of incoming samples in accordance with a control signal from the control module (27). The output of the sign modifying module (29) splits into two paths (30a, 30b). The first path (30a) includes the first and second delay elements (31, 33) and the first multiplying means (35). The second path (30b) includes the second multiplying means (37). In the first path (30a), samples outputted from the sign modifying module are delayed by two clock periods by the first and second delay elements (31, 33), each delay element delaying throughput of the samples by one clock period. The first and second multiplying means (35, 37) are arranged to multiply applied input samples by one of two different weighting factors. Finally, the outputted samples from the first and second multiplying means (35, 37) are each fed to the summing module (39) whereby the value of the output samples are added together.</p> |
