INTEGRATED CIRCUIT TESTING SYSTEM AND METHOD

摘要

A system and method for testing an integrated circuit at low speed is described herein. The method uses at least two parallel circuits comprising a data circuit and a clock circuit, wherein these parallel circui ts are provided with at least one inverter for sensing the feeding current of each circuit so as to obtain current pulses that are transformed into binary signals forwarded to a tester that measures the delay time between these signals.