发明名称 |
Operable synchronous semiconductor memory device switching between single data rate mode and double data rate mode |
摘要 |
A synchronous semiconductor memory device operates an input/output buffer circuit in synchronization with an external clock signal in a single data rate SDRAM operation mode. In a double data rate SDRAM operation mode, an internal clock signal of a frequency two times that of the external dock signal is generated. The input/output buffer circuit is operated in synchronization with the internal dock signal.
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申请公布号 |
US2003103407(A1) |
申请公布日期 |
2003.06.05 |
申请号 |
US20030339288 |
申请日期 |
2003.01.10 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
OOISHI TSUKASA;ISHIKAWA MASATOSHI |
分类号 |
G11C11/413;G11C7/10;G11C11/407;(IPC1-7):G11C8/18 |
主分类号 |
G11C11/413 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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