发明名称 |
Heuristic for identifying loads guaranteed to hit in processor cache |
摘要 |
A heuristic algorithm which identifies loads guaranteed to hit the processor cache which further provides a "minimal" set of prefetches which are scheduled/inserted during compilation of a program is disclosed. The heuristic algorithm of the present invention utilizes the concept of a "cache line" (i.e., the data chunks received during memory operations) in conjunction with the concept of "related" memory operations for determining which prefetches are unnecessary for related memory operations; thus, generating a minimal number of prefetches for related memory operations.
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申请公布号 |
US6574713(B1) |
申请公布日期 |
2003.06.03 |
申请号 |
US20000685431 |
申请日期 |
2000.10.10 |
申请人 |
SUN MICROSYSTEMS, INC. |
发明人 |
KOSCHE NICOLAI;DAMRON PETER C. |
分类号 |
G06F9/45;G06F12/08;(IPC1-7):G06F12/00 |
主分类号 |
G06F9/45 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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