Frequency/Phase comparison circuit with gated reference and signal inputs

摘要

Disclosed is a frequency-locked loop (FLL), which attempts to bring about frequency and phase synchronization between two signals over the control bandwidth of the loop: a reference signal and a voltage-controlled oscillator (VCO) signal. For example, the FLL employs a reference signal generated by a crystal oscillator of frequency fREF and a VCO signal generated by the oscillations of an unquenched SRG resonator with tunable resonant frequency fRES. These signals are connected to the inputs of a phase/frequency detector (PFD) which produces output pulses in response to the relationship between fREF and fRES. These pulses are applied to a loop filter (LF) which creates a voltage using some kind of charge-storage element. This loop filter voltage is a so-called error voltage whose value is used to control the frequency of the resonator to bring the reference signal and VCO signal into phase synchrony.