发明名称 |
Memory interface protocol using two addressing modes and method of operation |
摘要 |
A memory interface (15) and method of use implements a cache (14) bursting addressing technique which begins a read of main memory (16) in a wrap around mode before automatically switching into a linear addressing mode. The use of two modes which automatically change eliminates an access delay to the main memory when switching modes and optimizes system performance by providing a most critical word first in a first cache line fill and advancing to a sequential address following the first cache line. The sequential address has a higher probability of next use by the processor than any other address. The automatic mode change may be overridden by the memory interface.
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申请公布号 |
US6574707(B2) |
申请公布日期 |
2003.06.03 |
申请号 |
US20010849704 |
申请日期 |
2001.05.07 |
申请人 |
MOTOROLA, INC. |
发明人 |
SHAW CRAIG D. |
分类号 |
G06F12/04;G06F12/08;(IPC1-7):G06F12/00 |
主分类号 |
G06F12/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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