发明名称 |
Method and apparatus for arithmetic operation on vectored data |
摘要 |
A method of multiplying 32-bit values includes decomposing each multiplicand into its 16-bit components. This approach leads to a processor core design which permits re-use of much of the logic in the multiplication unit. The multiplication unit includes a selector which can feed various-sized data formats to the same multiplier circuits. Multiple data transformation paths are provided and feed into a single compression circuit and a single configurable full adder circuit.
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申请公布号 |
US6574651(B1) |
申请公布日期 |
2003.06.03 |
申请号 |
US19990411620 |
申请日期 |
1999.10.01 |
申请人 |
HITACHI, LTD. |
发明人 |
CUI JEFFREY;ROSSIGNOL STEPHANE;CHUA-EOAN LEW G. |
分类号 |
G06F7/00;G06F7/52;G06F9/305;G06F17/16;H04N7/30;(IPC1-7):G06F7/38 |
主分类号 |
G06F7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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