发明名称 |
Computer cache system with deferred invalidation |
摘要 |
A lower level cache detects when a line of memory has been evicted from a higher level cache. The lower level cache stores the address of the evicted line. When the system bus is idle, the lower level cache initiates a transaction causing all higher level caches to invalidate the line. The lower level cache then places the line into a special state. If a line in the special state is evicted from the lower level cache, the lower level cache knows that the line is not cached at a higher level, and therefore a back-invalidate transaction is not needed.
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申请公布号 |
US6574710(B1) |
申请公布日期 |
2003.06.03 |
申请号 |
US20000629128 |
申请日期 |
2000.07.31 |
申请人 |
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. |
发明人 |
GAITHER BLAINE D.;HERRELL RUSS W |
分类号 |
G06F12/08;G06F15/16;G06F15/177;(IPC1-7):G06F12/00 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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