发明名称
摘要 A latch circuit includes a first circuit including an N-MOS transistor having a first electrode receiving a signal, a second electrode outputting the signal, a gate electrode, and a P-well, and a first inverter including input and output terminals. The second electrode of the N-MOS transistor is electrically connected to the input terminal of the first inverter, and the gate electrode of the N-MOS transistor is electrically connected to the P-well of the N-MOS transistor.
申请公布号 KR100379607(B1) 申请公布日期 2003.06.02
申请号 KR19990044567 申请日期 1999.10.14
申请人 发明人
分类号 H03K3/356;H03K19/00;H03K3/037 主分类号 H03K3/356
代理机构 代理人
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