CLOCK BUFFER CIRCUIT HAVING CLOCK TUNING SCHEME

摘要

PURPOSE: A clock buffer circuit having a clock tuning scheme is provided to tune easily a clock signal by generating slowly or rapidly an output clock signal in response to an input clock signal. CONSTITUTION: A clock path includes the first to the third inverters(INV11-INV13) connected between an input clock signal and an output clock signal in order to transmit the input clock signal. The first portion is connected with the clock path in order to output slowly a phase of the input clock signal in response to the first control signal. The first circuit portion is formed with the first and the second delay circuits(110,120). The second portion is connected with the clock path in order to output rapidly the phase of the input clock signal in response to the second control signal. The second circuit portion is formed with the first and the second stack inverters(INV14,INV15). A control circuit(130) generates the first and the second control signals.