发明名称 |
HIGH-SPEED HARDWARE CRYPTOGRAPHIC PROCESSING SYSTEM AND METHOD THEREOF |
摘要 |
PURPOSE: A high-speed hardware cryptographic processing system and a method thereof are provided to enhance the performance of a cryptographic process by performing a symmetric key and an asymmetric key ciphering algorithm in parallel. CONSTITUTION: A scheduler(120) is used for generating the scheduling information for an executing procedure of a ciphering algorithm. A storage portion(130) stores rearranged command, rearrangement information, and the address information of the cryptographic data according to the scheduling information. A cryptographic processing portion(150) reads the stored data of the storage portion and performs a cryptographic process according to the command priority by referring to the command rearrangement information and the address information. A control portion(140) outputs a command to generate the scheduling information, sort cryptographic data, assign the data, and perform the cryptographic process.
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申请公布号 |
KR20030043447(A) |
申请公布日期 |
2003.06.02 |
申请号 |
KR20010074630 |
申请日期 |
2001.11.28 |
申请人 |
ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE |
发明人 |
CHOI, YONG JE;JUNG, GYO IL;KIM, HO WON;KIM, MU SEOP;PARK, YEONG SU |
分类号 |
H04L9/14;(IPC1-7):H04L9/14 |
主分类号 |
H04L9/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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