| 摘要 |
PURPOSE: A multi-port semiconductor memory device having a reduced bit line voltage offset and a method for arraying memory cells of the same are provided to improve an operating speed and reduce the power consumption by removing or reducing largely the bit line voltage offset. CONSTITUTION: A plurality of memory cells(811,812,813,814) include the first bit line couples and the second bit line couples, respectively. A plurality of flipped memory cells(821,822,823,824) include the first flipped bit line couples and the second flipped bit line couples, respectively. The memory cells and the flipped memory cells are arrayed in a row direction, alternately. A preliminary memory(831) is installed between the memory cells and the flipped memory cells at a predetermined position of the row direction. The memory cells and the flipped memory cells are 8 transistor memory cells.
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