发明名称 CLOCK WIRING STRUCTURE AND ADJUSTING METHOD FOR CLOCK TRANSMISSION DELAY TIME
摘要 PROBLEM TO BE SOLVED: To provide a clock wiring structure which makes it easy to adjust the clock skew. SOLUTION: Along a clock wire 1, a couple of shield wires 2 are arranged on both sides in parallel and along the clock wire 1 and shield wires 2, shield wires 3 are provided below them in parallel. The shield wires 2 and 3 are connected to the ground of a semiconductor integrated circuit. The clock skew is eliminated by adjusting the transmission delay time of a signal in the clock wire 1 by varying the line width of the shield wires 2 and varying the wiring capacitance of the clock wire 1.
申请公布号 JP2003158186(A) 申请公布日期 2003.05.30
申请号 JP20010355211 申请日期 2001.11.20
申请人 NEC CORP 发明人 OKADA KEIICHI
分类号 G06F17/50;H01L21/3205;H01L21/82;H01L21/822;H01L23/52;H01L27/04;(IPC1-7):H01L21/822;H01L21/320 主分类号 G06F17/50
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