发明名称 |
SEMICONDUCTOR INTEGRATED CIRCUIT |
摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit that can create diversified logic states without generating test obstruction factors and can easily execute an IDDQ test having a high diagnosis rate. SOLUTION: The semiconductor integrated circuit comprises an obstruction factor cancellation circuit for individually or forcibly cancelling the test obstruction factors of a floating state or the like to be generated in each section of an integrated circuit when a circuit stops, and a test mode generation circuit 5 for supplying an IDDQ mode signal 12 for making active a circuit to the obstruction factor cancellation circuit for generating a test mode.
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申请公布号 |
JP2003156534(A) |
申请公布日期 |
2003.05.30 |
申请号 |
JP20010355439 |
申请日期 |
2001.11.21 |
申请人 |
HITACHI LTD;HITACHI INFORMATION TECHNOLOGY CO LTD;HITACHI ULSI SYSTEMS CO LTD |
发明人 |
UCHIDA MINORU;HIBI KAZUO;HAYAKAWA AKIO |
分类号 |
G01R31/26;G01R31/28;H01L21/822;H01L27/04;(IPC1-7):G01R31/28 |
主分类号 |
G01R31/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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