| 摘要 |
PROBLEM TO BE SOLVED: To improve integration factor of a chip by decreasing the number of test bits for the number of information bits. SOLUTION: A semiconductor memory is provided with an ECC circuit 103 provided with an encoder generating a test bit ECC for error correction for data written in a plurality of memory cell area 1010 -1017 and adding them and a decoder performing error correction processing for data read out from the memory cell area 1010 -1017 using a generated test bit ECC between I/O terminals 1040 -1047 and page buffers 1020 -1027 . The ECC circuit 103 allots a test bit ECC of 40 bits making 4224 bits being eight times of 528 bits being write and read units for one memory cell area 101j as information bit length, and performs encoding processing and decoding processing with 8 bits in parallel. |
