| 摘要 |
<p>A processing architecture for performing a plurality of tasks comprises a conveyor of pipe stages, having a certain width comprising different fields including commands and operands, and a clock signal; wherein each pipe stage performs a certain part of an operation for each task of the plurality in a respective time slot. The processing architecture is also implemented in random access memory and dynamic random access memory devices. The present invention provides processing of data such that latency of memory and communication channels does not reduce the performance of the processor.</p> |
