| 摘要 |
A reconfigurable logic device according to the invention comprises a lookup table (LUT) (11.1) with an input (in1) for receiving an input signal and an output (out) for providing a binary output signal. The reconfigurable logic device is characterized by, a control input (ctrl) for receiving a control signal, a controllable inverting gate (11.2) for providing the address signal to the LUT (11.1) in response to the control signal and the input signal, and by a controllable inverting gate (11.3) for providing a modified output signal in response to the output signal of the LUT and the control signal. The reconfigurable logic device according to the invention can operate at a high speed, and at the same time have a relatively modest configuration memory. |
