发明名称 Hold time error correction method and correction program for integrated circuits
摘要 A hold time error list, having for each hold time error path a hold time error value satisfying plural timing constraints, and more specifically a maximum hold time error value for each of timing constraints, as well as a setup time margin map allocating to path a setup time margin satisfying plural timing constraints for each setup time error path, and more specifically minimum value of setup time margins for the same path for each timing constraint, are generated. Also, referring to this setup time margin map, delay buffers, which reduces or eliminates hold time error of hold error list, and a delay of which is within the range of delay amounts and positions equal to or lower than the setup time margin, are inserted. Referring to the setup time margin map, it is possible to insert delay buffer to correct hold time error without causing new setup time errors.
申请公布号 US2003101399(A1) 申请公布日期 2003.05.29
申请号 US20020270111 申请日期 2002.10.15
申请人 FUJITSU LTD 发明人 YOSHIKAWA SATORU
分类号 G06F1/10;G06F1/12;G06F17/50;H01L21/82;(IPC1-7):G06F17/50;G01R31/28;G06F11/00 主分类号 G06F1/10
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