| 摘要 |
The present invention discloses a universal clock generator, which comprises a high frequency clock region for generating high frequency clocks and a low frequency clock region for generating high frequency clocks. The low frequency clock region includes at least one delay lock loop for increasing the number of high frequency clocks of the high frequency clock region. When the number of high frequency clocks (such as a CPU clock, SDRAM clock, AGP clock and PCI clock) is not enough, the delay lock loop of the low frequency clock region can be cascaded to support insufficient clocks.
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