| 摘要 |
A programmable interface for FPGA cores embedded in an integrated circuit. The interface has an interconnect multiplexer (which includes demultiplexers) connected to the FPGA core and other elements of the integrated circuit. A control portion of the interface provides selection control bits to the interconnect multiplexer to make the desired connection configuration. Programmable latches in the control portion hold the selection bits which are loaded into the latches at the same time configuration bits are loaded into the integrated circuit to program the FPGA core. Alternatively, the control portion can be implemented by another FPGA core which is configured as a state machine to generate the selection control bits.
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