发明名称 |
A power failure safe architecture |
摘要 |
A component powered by a first power supply activates a driving signal. The driving signal indicates that both a second power supply voltage has a magnitude greater than a reference voltage and an enable signal is active. A driver transfers the output signal when the driving signal is active. In a multi-processor computer system implementation, each of two processor cores are independently supplied power by each of two core power supplies while a single I/O power supply supplies power to the I/O rings of both processors. Each processor includes a bus isolation circuit to prevent its respective processor from loading the system bus in the event that a core power supply fails. |
申请公布号 |
GB2357872(B) |
申请公布日期 |
2003.05.28 |
申请号 |
GB20010005291 |
申请日期 |
1999.09.07 |
申请人 |
* INTEL CORPORATION |
发明人 |
ALPER * ILKBAHAR;CHRISTOPHER * CHENG |
分类号 |
G06F1/26;G06F1/30;G06F11/00;(IPC1-7):G06F1/26;G06F13/00;G06F13/38;G06F11/30 |
主分类号 |
G06F1/26 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|