| 发明名称 |
Graphics processor architecture |
| 摘要 |
<p>A discrete cosine transform (DCT) or inverse discrete transform (IDCT) apparatus and method, comprising a transpose memory unit and an arithmetic circuit interconnected with said transpose memory unit, said arithmetic circuit including a combinatorial circuit for calculating a DCT or IDCT without a clocked storage unit.</p> |
| 申请公布号 |
EP0875853(A3) |
申请公布日期 |
2003.05.28 |
| 申请号 |
EP19980303352 |
申请日期 |
1998.04.29 |
| 申请人 |
CANON KABUSHIKI KAISHA |
发明人 |
GIBSON, IAN;LONG, TIMOTHY MERRICK;AMIES, CHRISTOPHER |
| 分类号 |
G06F9/38;G06F17/14;G06T1/20;G06T9/00;G06T15/00;G11C7/10;H04N7/26;(IPC1-7):G06T1/20 |
主分类号 |
G06F9/38 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
|
| 地址 |
|
