| 摘要 |
PURPOSE: A device and a method for controlling interrupt are provided to reduce an overhead time needed to check the interrupt occurrence for various interrupt sources. CONSTITUTION: A control part(201) controls the entire operations of an interrupt controller(200). A mask register(202) masks or unmasks the interrupt source input. A 2-level priority register(203) assigns a priority for the same interrupt. An interrupt address value register(204) stores an address value for the highest priority interrupt source assigned by the priority set by an initial design and the 2-level priority register(203). A direction register(207) decides whether each interrupt source operates an FIQ(Former Interrupt reQuester) or an IRG(Interrupt Requester). An FIQ and an IRQ state register(208,209) display the active state of an allotted interrupt source. An FIQ and an IRG mask register(210,211) mask or unmask an interrupt request signal inputted to a processor. A state clear register(212) clears a value of the corresponding interrupt state register in case that the trigger mode of the interrupt source input is an edge trigger mode.
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