Phase locked loop using sample and hold after phase detector

摘要

The present invention provides a phase locked loop (10) for generating a variable output frequency signal. The phase locked loop (10) includes a controlled oscillator (14) to generate the variable output frequency signal in response to a tune signal. A feedback frequency divider (16) coupled to the controlled oscillator (14) is operable to generate a divided frequency signal from the variable output frequency signal. A phase detector (18) generates an error signal representing a difference between a reference frequency signal and the divided frequency signal. A sample and hold circuit (22) is activable in response to a gating signal (20) derived from the reference frequency, to sample the error signal and generate a sampled signal. A loop filter (12) filters the sampled signal and generates the tune signal.