发明名称 |
Digital clocking synchronizing mechanism |
摘要 |
A telephone switching system regenerates a clock signal transmitted from control equipment to peripheral equipment. The switching system receives a clock signal from the control equipment at the peripheral equipment. The clock signal is compared to a reference clock signal generated at the peripheral equipment to determine a phase error. The phase error is accumulated over a time period as determined by the peripheral equipment. The system adjusts the modulo of a ring counter as a function of the accumulated phase error. The output of the ring counter can then be used in timing functions within the peripheral equipment.
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申请公布号 |
US6570982(B1) |
申请公布日期 |
2003.05.27 |
申请号 |
US19990343689 |
申请日期 |
1999.06.30 |
申请人 |
TELTRONICS, INC. |
发明人 |
WEIR STEPHEN |
分类号 |
H04J3/06;H04L7/033;H04M3/10;H04M3/12;H04M19/00;H04Q1/04;H04Q1/10;H04Q11/04;(IPC1-7):H04M3/00;H03D3/24 |
主分类号 |
H04J3/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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