发明名称 Semiconductor mask alignment system utilizing pellicle with zero layer image placement indicator
摘要 An exposure apparatus is provided for a semiconductor wafer, which includes a light source, a body containing the light source, and an illumination optical system for directing light from the light source to the semiconductor wafer. A holder in the body holds a reticle and a zero layer reticle is disposed between the illumination optical system and the light source for masking light from the light source. The zero layer reticle has a pellicle frame and a pellicle film with a zero layer image placement indicator thereon.
申请公布号 US6569579(B2) 申请公布日期 2003.05.27
申请号 US20010805846 申请日期 2001.03.13
申请人 CHARTERED SEMICONDUCTOR MANUFACTURING, LTD. 发明人 GHOSH AMIT;TAN YEW KONG
分类号 G03F7/20;G03F9/00;(IPC1-7):G03F9/00 主分类号 G03F7/20
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