发明名称 Semiconductor memory having refresh function
摘要 An internal row address signal is generated by a refresh address counter and supplied to a row decoder. In a normal refresh operation, the refresh address counter sequentially increments the internal row address signal on the basis of a trigger signal. As a result, the data in all memory cells is refreshed. In a low-consumption-current refresh operation, at least one of the bits of the internal row address signal is fixed. Hence, the refresh operation is executed only for the memory cells of a predetermined refresh area.
申请公布号 US6570801(B2) 申请公布日期 2003.05.27
申请号 US20010981517 申请日期 2001.10.16
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 YOSHIDA MUNEHIRO;SHINYA HIROSHI
分类号 G11C11/407;G11C11/406;(IPC1-7):G11C7/00 主分类号 G11C11/407
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