发明名称 Low via resistance system
摘要 A method of forming a metallization interconnection system within a via. A first liner layer of titanium is deposited to a first thickness in the following manner. A substrate containing the via is placed within an ion metal plasma deposition chamber that contains a titanium target. The ion metal plasma deposition chamber is evacuated to a first base pressure. A first flow of argon is introduced to the ion metal plasma deposition chamber at a first deposition pressure. The substrate is biased to a first voltage. A plasma within the ion metal plasma deposition chamber is energized at a first power for a first length of time. A second liner layer of TixNy is deposited to a second thickness on top of the first liner layer of titanium in the following manner. A first flow of nitrogen and a second flow of argon are introduced to the ion metal plasma deposition chamber at a second deposition pressure. The substrate is biased to a second voltage. The plasma within the ion metal plasma deposition chamber is energized at a second power for a second length of time, after which the substrate is removed from the ion metal plasma deposition chamber. Finally, a third liner layer of titanium nitride is deposited in a second deposition chamber, and a plug of tungsten is deposited.
申请公布号 US6569751(B1) 申请公布日期 2003.05.27
申请号 US20000617550 申请日期 2000.07.17
申请人 LSI LOGIC CORPORATION 发明人 TRIPATHI PRABHAKAR P.;WANG ZHIHAI;LI WEIDAN
分类号 C23C14/02;C23C14/06;C23C14/34;H01L21/285;H01L21/768;(IPC1-7):H01L21/28;H01L21/44;H01L21/476 主分类号 C23C14/02
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