发明名称 Method of fabricating an integrated circuit
摘要 The invention provides a technology for reducing the direct contact resistance and for reducing the junction leak while maintaining the punch through margin. A semiconductor integrated circuit device is provided which comprises: a substrate; a transistor formed on the substrate, which comprises a source, a drain and a gate which controls a current flowing from said source to said drain; and a contact plug being electrically connected to at least one of the source and drain and made of a conductive material including a dopant. The contact plug is formed of at least a first layer and a second layer. The first layer contacts with one of the source and drain and is made of said material including the dopant of a first concentration. The second layer is formed of a layer of said material including the dopant of a second concentration, which is lower than the second concentration.
申请公布号 US6570233(B2) 申请公布日期 2003.05.27
申请号 US20010901071 申请日期 2001.07.10
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 MATSUMURA AKIRA
分类号 H01L21/28;H01L21/285;H01L21/336;H01L21/768;H01L21/8242;H01L23/522;H01L27/108;(IPC1-7):H01L21/338;H01L21/425;H01L31/119 主分类号 H01L21/28
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