发明名称 |
Multiple input phase lock loop with hitless reference switching |
摘要 |
A clock recovery circuit for recovering clock signals from one of a plurality of input reference signals, includes an acquisition phase locked loop (PLL) for each input. The acquisition PLL having phase comparator for comparing the phase of an input signal to a feedback signal, and first and second digital controlled oscillators (DCOs) receiving an input from the phase comparator. The first DCO of the acquisition PLL is in a feedback loop to supply an input to the phase comparator and the second DCO of the acquisition PLL has a control input to introduce a phase offset therein relative to said the DCO of the acquisition PLL and provides an output for the acquisition PLL. An output PLL has a phase comparator selectively connectable to the output of each of the acquisition PLLs. The output PLL has a first DCO providing an output for the circuit and a second DCO in a feedback loop providing a feedback signal to the phase comparator of the output PLL. The second DCO of the output PLL has a control input to introduce a phase offset therein relative to the first DCO of the output PLL. A control unit for sets the phase of the second DCO of the acquisition circuit and the second DCO of the output PLL to a common value during changeover from one input to another to avoid an instantaneous phase error upon switching reference signals.
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申请公布号 |
US6570454(B2) |
申请公布日期 |
2003.05.27 |
申请号 |
US20010004801 |
申请日期 |
2001.12.07 |
申请人 |
ZARLIAK SEMICONDUCTOR INC. |
发明人 |
SKIERSZKAN SIMON |
分类号 |
H03L7/06;H03L7/07;H03L7/08;H03L7/081;H03L7/099;H04J3/06;(IPC1-7):H03L7/06;H03L7/085;H03L7/093 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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