| 摘要 |
The present invention relates to a NAND-type memory array and method of reading, programming and erasing the same. In order to solve a problem that a reading speed is lowered due to a large well loading upon a reading operation as the well and the bit line are connected in order to apply a negative bias upon a programming operation and a positive bias upon an erasure operation in a NAND-type memory array using a dip trench isolation (DTI) scheme, the present invention separates the well and the bit line by additionally including a well node for applying a bias to the well upon an erasure and reading operation, a triple well select gate for selecting the well node, and a program well select gate for applying a bias to the well via the bit line upon a programming operation. Therefore, the present invention can lower in the speed upon a reading operation.
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