| 摘要 |
PROBLEM TO BE SOLVED: To simultaneously satisfy a jitter transfer standard specified by ITU-T and a jitter tolerance standard and to expand a degree of freedom in design. SOLUTION: This device is provided with a phase-locked loop (PLL) 103 for generating a first clock signal synchronized to the frequency of a data signal to be inputted and phase-locked to the change point of the relevant data signal and a PLL 104 for generating a second clock signal frequency- synchronized and phase-locked to the first clock signal. Then, the upper limit value of a jitter pass frequency in the PLL 103 to transmit a jitter signal superimposed on the inputted data signal to the first clock signal without suppression is equal to or higher than the upper limit value of a jitter pass frequency required to the relevant device, and the upper limit value of a jitter pass frequency from the PLL 103 to the PLL 104 to transmit the jitter signal superimposed on the inputted data signal to the second clock signal without suppression is equal to or lower than the upper limit value of a jitter pass frequency required to the relevant device. |
