发明名称 PHASE-LOCKED LOOP CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a phase-locked loop circuit which can suppress jitters of the phase generated from the output of its voltage-controlled oscillator. SOLUTION: In the phase-locked loop circuit, by delaying respectively a reference signal 81 and a feedback signal 91 with delay circuits 71, 72, and by comparing with each other the phases of a delayed reference signal 82 and a delayed feedback signal 92, the phase difference between them is converted into a current by a second charge-pump circuit 22 so as to make the current flow in a low-pass filter 31. Thereby, the response current to the phase difference can be also made to flow in the low-pass filter 31 in a delayed timing so as to increase the number of the pulse currents for conducting charging/ discharging of the capacitor of the low-pass filter 31.
申请公布号 JP2003152532(A) 申请公布日期 2003.05.23
申请号 JP20010348127 申请日期 2001.11.14
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SAKASHITA TOSHIHIKO
分类号 H03L7/087;H03L7/107 主分类号 H03L7/087
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