发明名称 DESIGN METHOD FOR ELECTRONIC APPLIANCE PROVIDED WITH CLOCK FREQUENCY MODULATION CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To decide design specifications of an optimum clock frequency modulation circuit considering both of clock specifications and an EMI suppression effect amount and to shorten a development period of a device to which the clock frequency modulation circuit is applied by obtaining an estimated value of the EMI suppression effect amount by the clock frequency modulation circuit in an EMI standard adaptability test after the device is completed in a stage of deciding the design specifications of the clock frequency modulation circuit. SOLUTION: The design specifications of the clock frequency modulation circuit satisfying the clock specifications 53 which are electric specifications of clock signals and satisfying an EMI effect target value 58 for which an EMI suppression effect in the EMI standard adaptability test 21 is estimated are decided in SSC specification decision 14. Thus, re-design or the like due to insufficiency of the EMI suppression effect in an EMI evaluation after the device is completed is eliminated and the development period is shortened.</p>
申请公布号 JP2003150660(A) 申请公布日期 2003.05.23
申请号 JP20010348890 申请日期 2001.11.14
申请人 NEC CORP 发明人 YAMADA TOMONORI
分类号 G06F17/50;G06F1/04;(IPC1-7):G06F17/50 主分类号 G06F17/50
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