| 摘要 |
PROBLEM TO BE SOLVED: To increase data transfer speed in a SDRAM having posted CAS specifications in which timing from input of an ACTV command to input of a READ command can be selected arbitrarily. SOLUTION: A memory cell array is constituted of two sub-arrays 17i, 17j which can perform independently activation. When a READ command in inputted one clock cycle after an ACTV command is inputted, a row decoder 22 activates only a sub-array having a memory cell selected by a row address AX and a column address AY out of the sub-array 17i, 17j, and performs read- out operation of data. Thereby, as a region required to activate can be narrowed comparing with conventional semiconductor memory, load of a power source is reduced, a time required for that voltage of the bit line reaches to the prescribed voltage is shortened when data of the bit line is amplified, and read-out speed of data is increased.
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