发明名称 INTERLEAVING ORDER GENERATOR, INTERLEAVER, TURBO ENCODER AND TURBO DECODER
摘要 PROBLEM TO BE SOLVED: To provide a means for realizing an internal interleaver of a turbo decoder, which is used for a mobile communication system with a relatively small amount of memory. SOLUTION: The data length corresponds to R pieces of blocks, each of which has a length of p and is based on a prime number p. A means 201 is provided for generating R pieces of different integer numbers q0 , q1 , q2 ,..., qR-1 which are mutually disjoint from p-1 and elements of a finite field, whose characteristic is the prime number p as power of the integer numbers with respect to primitive elementsν, such asνto the power of q0 ,νto the power of q1 ,νto the power of q2 , ...νto the power of qR-1 (mod p). The means 201 then raises the elements to the j-th power on the finite field for generating (νto the power of q0 )<j> , (νto the power of q1 )<j> , (νto the power of q2 )<j> ,... (νto the power of qR-1 )<j> (mod p) in real time. Shuffling of the 0-th order is performed by sequentially adding 1 to the p-fold value of the output from a block shuffling pattern recording means 205. Shuffling of the j-th order is performed by repeating the operation of adding the value generated by the means 201 to the p-fold value of the output from the means 205, with respect to j=1 to (p-2).
申请公布号 JP2003152551(A) 申请公布日期 2003.05.23
申请号 JP20010353675 申请日期 2001.11.19
申请人 NEC CORP 发明人 MARU TSUGIO
分类号 H03M13/23;H03M13/27;H03M13/29;H03M13/45;H04B1/707;H04J13/00;H04L1/00 主分类号 H03M13/23
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