SEMICONDUCTOR MEMORY DEVICE AND BIT LINE SENSING METHOD THEREOF

摘要

PURPOSE: A semiconductor memory device is provided to be capable of easily controlling a bit line sensing operation without increasing a layout area. CONSTITUTION: A cell bit line precharge circuit(40) precharges a cell bit line pair(BLcell,BLBcell) by a voltage lower than the first voltage in response to a cell bit line precharge control signal(BLPRE). An SA(Sense Amplifier) bit line precharge circuit(44) precharges an SA bit line pair(BLsa,BLBsa) by the first voltage in response to an SA bit line precharge control signal(SAPRE). A charge transfer circuit(42,50) transfers charges between the cell bit line pair and the SA bit line pair in response to a control signal. The first sense amplifier circuit(46) amplifies a voltage of the SA bit line pair by the first voltage. The second sense amplifier circuit(48) amplifies a voltage of the SA bit line pair by the second voltage in response to an SA enable signal.