| 摘要 |
The integrated circuit in the form of a micro-controller (MC) comprises at least one element such as a central processing unit (CPU) timed by a clock signal (CK1) delivered by a first oscillator (OSC1), the means which include the central processing unit (CPU) and a memory program store (MEM) for halting the first oscillator, a timing device (TCT) which is autonomous with respect to the first oscillator, the means which include a control register (CREG) for starting the timing device at the time of halting the first oscillator, and an interruption decoder (ITDEC) for reactivating the first oscillator by the intermediary of the CPU. The ON/OFF input of the first oscillator (OSC1) receives a HALTS signal delivered by the CPU. The timing device (TCT) comprises the means for delivering a reactivation signal (ITCT) by the intermediary of the interruption decoder (ITDEC) in the form of an interruption request signal (IRQ). The autonomous timing device (TCT) is timed by a second oscillator (OSC2) which has a lower electrical consumption than the first oscillator. The first oscillator (OSC1) is a quartz oscillator, and the second oscillator (OSC2) is of type RC. The timing device (TCT) is started by the HALTS signal delivered by the CPU and is a function of at least one control bit such as enable (E) stored in the control register (CREG). The timing device (TCT) comprises the frequency dividers or prescalers (PSC1,PSC2) receiving the second clock signal (CK2), a calibration register (AWUREG) for storing the division factor (N), a calibration circuit (TIMPER) for recalling the divider circuit outside the halt periods of the first oscillator, and a circuit connected to the OFF/ON input of the second oscillator (OSC2) which comprises an OR gate (G1), two AND gates (G2,G3), and an inverter (INV). The method for controlling the length of the halt period in an integrated circuit is implemented by the micro-controller (MC).
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